Design and Development of ASIC
Design and Development of ASIC
The tech team of EmBestor Technology has many years of experience in designing and developing the flash IC controller and specializes in the flash memory storage system and its applications.
We currently have several dozens of successful development projects, which demonstrates our expertise and experience in process technology, design methodology, package, testing and HW/FW/SW Integration. In addition, EmBestor Technology also dedicates itself to developing new products and technology with all its resources, as well as strategies for new application market. These professional efforts will help customers creating their own ASIC products.
Generally speaking, the most critical step in the development of ASIC IC controllers is the process of designing IC controllers. The whole designing process can be divided into two parts: front-end design (a.k.a. logic design) and rear-end design (a.k.a. physical design).Front-end design flow
Front-end design flow
1. Specification planning
According to the design requested by customers, including the actual functions and capabilities of chips, we make a list of required functions to plan the appropriate specification of chips.
2. Architecture planning
According to the specification requested by customers, we propose the design resolution and the actual architecture for the modular functions.
3. HDL coding
We will use the hardware description languages (Verilog HDL or VHDL) to implement the modular functions by these codes. That is to say, we describe the actual hardware circuit by the HDL language to conclude the RTL (register transfer layer) codes.
4. Simulation verification
Simulation verification is to verify the correctness of codes for design. The verification criterion is the conformation to the original specification. It checks if all the requirements in specification, the only and ultimate standard for the design, are fulfilled. If not, the design and codes will need to be corrected. The design and simulation verification will be repeated several times until all the requirements in specification are fulfilled.
5. Logic synthesis
After the verification is completed, logic synthesis will then be implemented. Logic synthesis is to transform the HDL codes for implementing the design into the gate level netlist. It needs to set up the appropriate constraints, including the parameters of circuit area and timing. Logic synthesis is implemented based on the specific cell library. The parameters of circuit area and timing for the standard cell in every library are different. After the synthesis is completed, simulation verification needs to be implemented again to verify the correct transformation.
6. Timing analysis
Static timing analysis (STA) is part of the verification. It mainly verifies the circuit on timing to check if the controller violates the setup time and hold time. This step ensures that the timing function of chips conforms to the specification for the design.
7. Form verification
This step is critical in the verification process because it verifies the synthesized netlist on functions. It compares the synthesized netlist with the verified HDL design to check if it remains functional equivalence. The purpose of this step is to ensure that the original function of the circuit in the HDL description is not altered during the process of logic synthesis.
Back-end design flow
1. Design for test
Design for test (DFT) is to take tests in the future into the consideration in designing the chip. During the design step, the test circuit can be integrated into the chip, such as scanning chains.
2. Layout planning
Layout is the arrangement of the macro cell modules in chips, which determines the locations of all functional circuits, such as I/O pins, IP modules and memory cells. The layout planning will determine the final area of chips.
3. Clock tree synthesis
Clock tree synthesis (CTS) is the planning of the clock. The clock signals are transmitted to all register units in a symmetric way in digital chips, which can minimize the difference of clock latency for the same clock signal to all register units.
4. Layout and routing
Layout and routing refer to the planning of signal transmission, including the routing between all standard units (circuits of basic logic gates).
5. Retrieval of parasitic parameters
Because some effects, such as signal noise, cross-talk and reflection, may be caused inside chips by the resistance and the inductance coupling capacitances between adjacent cables, signal integrity may be compromised to change the signal voltage, which may cause false signals at its worst scenario. Analytic verification is implemented by the retrieval of parasitic parameters. It is extremely critical to verify the signal integrity.
6. Verification of the actual circuit layout
This step is to verify the actual circuit layout on functions and timing. Many tests need to be completed at the step, such as layout vs schematic (LVS), design rule checking (DRC) and electrical rule checking (ERC). These tests will check the consistency between the circuit layout and the gate circuit diagram after logic synthesis, the design rules (fulfilling the requirements for connection distance, connection width, etc.) and the electric regulations (checking the violations to open circuits and short circuits). Other aspects in back-end design include the analysis of power consumption on the circuit and the design for manufacturability (DFM) problems, which result from the development of manufacturing technology.
After the design of chips is completed, they can be produced. The actual circuit layout will be given to the foundry in the format of GDSII document. By the very complicated manufacturing process on the silicon wafers, the actual integrated circuits will be created. After the production of chips, specific packaging and testing procedures will then be implemented. After all these steps, chips can be shipped out for applications. By professional integration of HW/FW/SW design capability, we can provide customers with comprehensive solutions for ASIC system chips.